In data processing systems, a bus is commonly employed to interconnect various elements of the system. The bus is typically configured to optimize the performance of the data processing system. For example, a processor is connected to a main memory via a bus capable of carrying signals associated with the operation of each element. These signals include address, data and control signals of a type and quantity specific to the architecture of the processor.
As data processing systems achieve increasingly higher levels of performance, it is sometimes desirable to provide more than one processor and bus in the system. For example, it may be desired to provide a local bus which interconnects a host processor and a main memory, and to provide a remote bus which connects the local bus with an "intelligent" peripheral, such as a processor-based input/output controller. The peripheral processor may be of a different architecture from the host processor, thereby requiring a remote bus capable of carrying signals of a type and quantity different from those of the local bus.
In such multiple processor systems, it is essential to transfer signals between the local and remote buses, and to store, access and correctly interpret the signals, including data shared between them. In general, this requires a bus adapter that is connected to both buses and operates on each according to the characteristics of that bus. For example, the adapter must be able to receive data from a peripheral processor and transfer the data to memory locations addressable by the host processor. The host processor must then be able to access and correctly interpret the stored data.
A problem arises when the processors store and interpret particular data types in different formats. For character data types, all processors capable of interpreting ASCII character string formats store the data in a similar manner. However, there is a fundamental incompatibility in the way some processors store and interpret integer data types. For example, some processors store integer data in a format such that the least significant byte is interpreted at position in a 32-bit longword completely opposite that of other processors. That is, other processors interpret the byte in the same position as the most significant byte.
Prior attempts to resolve data type incompatibility between a peripheral processor sharing data with a host processor require software intervention to determine the data type and, if it was an integer data type, to direct the host processor to rearrange the data. Such a procedure resulted in data processing system performance degradation.
Therefore, in accordance with an aspect of the present invention, an object is to provide an apparatus for sharing data between processors having certain incompatible data formats.
Additionally, an object of the present invention is to provide a configurable data path between processors having certain incompatible data formats.
In accordance with another aspect of the invention, an object is to provide a programmable apparatus for configuring the data path between processors having certain incompatible data formats.